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Local anoidic oxidation lithography

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kurra.narendra posted on Wed, May 11 2011 7:29 AM

Dear Sir/Madam,

We would like ot know the details for executing lithography on the diInnova AFM system. We want to do local anodic oxidation of the surfaces.

Can you please give me some tricks in performinglithography repeatedly and reproducibly.

Thanks,

Narendra

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Answered (Not Verified) replied on Wed, May 11 2011 11:30 AM

Hi Narenda,

On the Innova you can to use the "Nanoplot" option for lithographic experiments. In order to start Nanoplot you simply "right click" on any previously acquired image and select the "send to Nanoplot" option. In the Nanoplot setting you want to select the type of lithography you would like to perform. In your case this may be "by voltage". You can now either draw the pattern you would like to create or import and previously created PS-level-1 pattern. There is a converter on your system for PS-level-1 compatible data. Hit "Etch" and your patetrn will be created. After doing so you can simply re-image your sample.

The commonly performed anodic oxidation on silicon requires a conductive tip and a clean Si-sample. Typical tip voltages are from -5V to -9V depending on the condition of your tip, the humidity level of your environment, and the quality of the sample. Scan speeds may be around 1um/s or so.

I suggest to write a few straight lines under varying conditions first to figure out the ideal conditions and the create the pattern you intend to.

Best,

Stefan

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saumil replied on Fri, Nov 11 2011 5:23 PM

Hi,

My question is related to anodic oxidation and lithography. I assume that we need the anodic oxidation stage carrier, which is not included. I would appreciate if anyone can help me with any literature/references for doing anodic oxidation or scratching 'using the diInnova'?

Thanks a lot.

 

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replied on Mon, Nov 14 2011 12:13 PM

Hi Saumil,

I have never seen an "anodic oxidation stage carrier" for the Innova. Now I am curious to know who told you that you need it.

The only requirement is that you can apply a voltage in between the tip and sample. That capability is build-in. Just take a clean piece of a silicon wafer and give it a go.

Stefan

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saumil replied on Mon, Nov 14 2011 1:23 PM

Hi Stefan,

Thanks a lot for replying. I was going through the diInnova SPM manual, page 189 Nanolithography section, where I saw the anodic oxidation "chip" carrier and its connection to the stage. I am sorry, I mistyped it as "stage carrier". http://www.brukerafmprobes.com/a-3449-00-107-0142.aspx

The student who uses the equipment said that it was not included in the system when it was bought. So I felt I should ask here.

As I gather from your reply, I can apply a bias without this part also?

Saumil

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replied on Tue, Nov 15 2011 11:14 AM

Hi Saumil,

That chip carrier that you pointed out allows you to bias the tip.

With the regular carrier the tip is always grounded. In order to apply a bias (which the software always allows) you have to route the bias voltage to the sample. So if you can live with biasing the sample you don't need any additional parts.

Stefan

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saumil replied on Tue, Nov 15 2011 11:33 AM

Stefan,

That sounds excellent. I can bias the sample with the opposite polarity then. This was good to know. I am only concerned about leakage currents/safety but I will see if that is a concern or not.

Thanks a lot

 

 

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saumil replied on Sat, Dec 10 2011 12:24 AM

Hello again Stefan,

My sample is not conductive since I have a 300nm oxide layer on top of Si. I understand that I need a path for current to flow, so the sample must be grounded) but people have reported oxidation results on graphene keeping the sample floating also (and applying negative bias to the tip ~-20V or so). Can I apply an external bias to the tip, instead of the +/-10V that can be done using the chip carrier and lead http://www.brukerafmprobes.com/a-3449-00-107-0142.aspx through the control software?

What is different if I simply connect the unmounted chip carrier to an external bias versus I use the chip carrier with lead (http://www.brukerafmprobes.com/a-3449-00-107-0142.aspx) ? Does this carrier provide isolation/insulation to the tip, which is normally grounded?

Thanks again.

 

 

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saumil replied on Sun, Dec 11 2011 12:22 AM

I think I understood it. Thanks.

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replied on Mon, Dec 12 2011 3:15 PM

The standard unmounted chip carrier is still connected to ground via the AFM head. The holder allowing for an external tip bias isolates the tip via a glass plate from the holder so that the tip can be biased. If you can supply me with a good graphene sample exhibiting mono- and bi layers I can supply you with a tip holder. Please contact me offline if interested. stefan.kaemmer at bruker-nano.com

Stefan

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